Design:
--Designing 8X1 mux with dataflow style modeling
Library ieee;
use ieee.std_logic_1164.all;
-- ****** Design under test (DUT)*******
--entity part
entity mux8X1_struct is
Port (
-- port interface
I : in STD_LOGIC_VECTOR (7 downto 0); -- input
s : in STD_LOGIC_VECTOR (2 downto 0); -- selection line
op : out STD_LOGIC); -- output
end mux8X1_struct;
-- architecture part
architecture Behavioral of mux8X1_struct is
-- component part
component mux4X1
-- component interface
Port (
I : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
en : in STD_LOGIC;
op : out STD_LOGIC);
end component;
-- signal decleration for the intermediate outputs
signal nt1, op1, op2: STD_LOGIC;
-- architecture body
begin
nt1 <= not s(2);
-- taking instance of the component
-- connection component -> design
-- I(3 downto 0) -> I(max downto min)
-- s(1 downto 0) -> s(max downto min)
-- en -> nt1/s(2)
-- op -> op
m1 : mux4X1 port map (I (3 downto 0), s(1 downto 0), nt1 ,op1);
m2 : mux4X1 port map (I (7 downto 4), s(1 downto 0), s(2),op2);
op <= op1 or op2;
end Behavioral;
_____________________________________________________________________
Test bench:
-- creating the test environment for 8X1 mux written in structural style modelling
Library ieee;
use ieee.std_logic_1164.all;
-- test bench entity
entity tb is
-- usually the test environment has no physical interface
-- Port ( );
end tb;
-- architecture part
architecture Behavioral of tb is
-- declare the DUT as a component
component mux8X1_struct
-- component interface
Port (
I : in STD_LOGIC_VECTOR (7 downto 0); -- input
s : in STD_LOGIC_VECTOR (2 downto 0); -- selection line
op : out STD_LOGIC); -- output
end component;
-- signal declaration for testbench interface
signal I : STD_LOGIC_VECTOR (7 downto 0);
signal s : STD_LOGIC_VECTOR (2 downto 0);
signal op : STD_LOGIC;
-- architecture body
begin
-- taking instace of DUT in testbench
-- connection DUT -> TB
-- op -> op
-- s (2 downto 0) -> s(2 downto 0)
-- I (7 downto 0) -> I(7 downto 0)
a1: mux8X1_struct port map (I(7 downto 0), s (2 downto 0),op);
-- generating test signals through process statement
process -- process with n sensitivity list
-- process body
begin
-- note: below combination genrate the output op always "high"
-- applying all possible combinations at selection line a
I<= x"01"; -- make 0th line high
s<= "000"; wait for 10 ns; -- select 0th line
I<= x"02"; -- make 1st line high
s<= "001"; wait for 10 ns; -- select 1st line
I<= x"04"; -- make 2nd line high
s<= "010"; wait for 10 ns; -- select 2nd line
I<= x"08"; -- make 3rd line high
s<= "011"; wait for 10 ns; -- select 3rd line
I<= x"10"; -- make 4th line high
s<= "100"; wait for 10 ns; -- select 4th line
I<= x"20"; -- make 5th line high
s<= "101"; wait for 10 ns; -- select 5th line
I<= x"40"; -- make 6th line high
s<= "110"; wait for 10 ns; -- select 6th line
I<= x"80"; -- make 7th line high
s<= "111"; wait for 10 ns; -- select 7th line
-- essential to add the assert fail line to reduce the size of VCD file
assert false report "end of simulation";
-- if you are not add this line simulation goes for infinitly
-- this line stops simulation after all test case mentioned above
wait;
end process;
end Behavioral;
_____________________________________________________________________
Testing the design:
EDA playground link: Click here
click here to refer the steps to execute the design and test bench on GHDL and GTKWave.
_____________________________________________________________________
Waveform:
Note:
1)as we are providing input I high according to the selection of line so we always get output high for all combinations of selection line input.
2) You can change any of the input I at the test bench and will see the change at output op.
_____________________________________________________________________
Dataflow design of 4X1 mux as a component:
--Designing 4X1 mux with dataflow style modeling
Library ieee;
use ieee.std_logic_1164.all;
-- ****** Design under test (DUT)*******
-- entity part
entity mux4X1 is
-- port interface of the mux4X1
Port (
I : in STD_LOGIC_VECTOR (3 downto 0); -- input
s : in STD_LOGIC_VECTOR (1 downto 0); -- selection line
en : in STD_LOGIC; -- enble signal
op : out STD_LOGIC); -- output
end mux4X1;
-- architecture part
architecture arch of mux4X1 is
-- signal decleration for the intermediate outputs
signal m : STD_LOGIC_VECTOR(3 downto 0);
-- architecture body
begin
m(0) <= (i(0) and (not s(1)) and (not s(0)) and en);
m(1) <= (i(1) and (not s(1)) and (s(0)) and en);
m(2) <= (i(2) and (s(1)) and (not s(0)) and en);
m(3) <= (i(3) and (s(1)) and (s(0)) and en);
op <= m(0) or m(1) or m(2) or m(3);
end architecture;
