Design 8X3 encoder using structural style modeling in VHDL and simulate on GHDL and GTKWave open simulator.

Design:

-- 8X3 encoder with structural style modeling
Library ieee;
use ieee.std_logic_1164.all;

-- *********Design under test(DUT)*******
-- entity part
entity Enco8X3 is
    -- port declaration part
    Port (
        -- input and output port declare in form of vector
        i : in STD_LOGIC_VECTOR (7 downto 0);
        y : out STD_LOGIC_VECTOR (2 downto 0));
end Enco8X3;

-- architecture part
architecture Behavioral of Enco8X3 is

-- we create the custom or4 gate for encoder   
component OR_4
    Port (
        -- port interface of the component
        i1,i2,i3,i4 : in STD_LOGIC;
        Y : out STD_LOGIC);
end component;

-- architecture in structural style
begin
-- use OR_4 as a component to realize the design
-- taking instace of the component or4 in architecture
a1: OR_4 port map (i(1),i(3), i(5), i(7), y(0));
a2: OR_4 port map (i(2),i(3), i(6), i(7), y(1));
a3: OR_4 port map (i(4),i(5), i(6), i(7), y(2));
end Behavioral;

Test bench:

 -- creating the test environment for 8X3 encoder written in structural style modelling
Library ieee;
use ieee.std_logic_1164.all;

-- test bench entity
entity tb is
-- usually the test environment has no physical interface
-- Port ( );
end tb;

-- architecture part
architecture Behavioral of tb is

-- declare the DUT as a component
component Enco8X3
    Port (
        -- component interface
        i : in STD_LOGIC_VECTOR (7 downto 0);
        y : out STD_LOGIC_VECTOR (2 downto 0));
end component;

-- signal declaration for testbench interface
signal i : STD_LOGIC_VECTOR (7 downto 0);
signal y : STD_LOGIC_VECTOR (2 downto 0);

-- architecture body
begin

-- taking instance of the component/DUT
--     connection DUT -> TB
--  i(7 downto 0 ) -> i(7 downto 0)
--  y (2 downto 0) -> y(2 downto 0)
a1: Enco8X3 port map (i, y);

-- test logic in process block
process
    begin
        i <= x"01"; wait for 10 ns;    -- i0 is high
        i <= x"02"; wait for 10 ns;    -- i1 is high
        i <= x"04"; wait for 10 ns;    -- i2 is high
        i <= x"08"; wait for 10 ns;    -- i3 is high
        i <= x"10"; wait for 10 ns;    -- i4 is high
        i <= x"20"; wait for 10 ns;    -- i5 is high
        i <= x"40"; wait for 10 ns;    -- i6 is high
        i <= x"80"; wait for 10 ns;    -- i7 is high

        -- essential to add the assert fail line to reduce the size of VCD file
        assert false report "end of simulation";
        -- if you are not add this line simulation goes for infinitly
        -- this line stops simulation after all test case mentioned above
        wait;
end process;
end Behavioral;

Testing the design:

EDA playground link: Click here

click here to refer the steps to execute the design and test bench on GHDL and GTKWave.

Waveform:

OR_4 component design:

Library ieee;
use ieee.std_logic_1164.all;

-- entity part
-- *********Design under test(DUT)*******
entity OR_4 is
    -- port declaration part
    Port (
        -- input and output port declare in form of vector
        i1,i2,i3,i4 : in STD_LOGIC;
        y : out STD_LOGIC);
end OR_4;

-- architecture part
Architecture struct of OR_4 is
-- signal assigned to the intermediate wires
signal y1,y2 : std_logic;
-- architecture body
begin
    y1 <= i1 or i2;
    y2 <= i3 or i4;
    y <= y1 or y2;
end struct;