Design 3X8 decoder using behavioural style modelling in VHDL and simulate on GHDL and GTKWave open simulator.

Design part:

--3X8 decoder using behavioral modelling
-- *********Design under test(DUT)*******

-- Entity part

entity Deco3X8 is
    Port (
        -- port declaration part    
            a : in STD_LOGIC_VECTOR (2 downto 0); -- input port declare as a vector
            o : out STD_LOGIC_VECTOR (7 downto 0)); -- output port declare as a vector
end Deco3X8;

-- Architecture part
architecture Behavioral of Deco3X8 is
-- architecture body
begin

-- behavioral block define in process
process (a)
begin
    -- based on input "a" output will be selected
    if (a = "000") then o <= x"01"; end if ; -- enable 0th line of output    
    if (a = "001") then o <= x"02"; end if ; -- enable 1st line of output
    if (a = "010") then o <= x"04"; end if ; -- enable 2nd line of output
    if (a = "011") then o <= x"08"; end if ; -- enable 3rd line of output
    if (a = "100") then o <= x"10"; end if ; -- enable 4th line of output
    if (a = "101") then o <= x"20"; end if ; -- enable 5th line of output
    if (a = "110") then o <= x"40"; end if ; -- enable 6th line of output
    if (a = "111") then o <= x"80"; end if ; -- enable 7th line of output
end process;
end Behavioral;

Test bench part :

Library ieee;
use ieee.std_logic_1164.all;

-- test environment for 3X8 decoder using behavioural modeling
-- test bench part
entity tb2 is
-- usually the test environment has no physical interface
-- Port ( );
end tb2;

-- architecture part
architecture Behavioral of tb2 is

-- declare DUT as a component in test bench
component Deco3X8
    -- port declaration part of the component
    Port (
        a : in STD_LOGIC_VECTOR (2 downto 0);
        o : out STD_LOGIC_VECTOR (7 downto 0));
end component;

-- declare the signals to interface with the ports
signal a : STD_LOGIC_VECTOR(2 downto 0);
signal o : STD_LOGIC_VECTOR(7 downto 0);

-- architecture body
begin

-- take the instance of the DUT in architecure body
D1: Deco3X8 Port map (a,o);
-- behaviour logic in process
    process
    -- process body
        begin
        -- generate signal to represent all possible combination after delay of 10ns
        a<="000";wait for 10 ns;
        a<="001";wait for 10 ns;
        a<="010";wait for 10 ns;
        a<="011";wait for 10 ns;
        a<="100";wait for 10 ns;
        a<="101";wait for 10 ns;
        a<="110";wait for 10 ns;
        a<="111";wait for 10 ns;
        
        -- essential to add the assert fail line to reduce the size of VCD file
        assert false report "end of simulation";
        -- if you are not add this line simulation goes for infinitly
        -- this line stops simulation after all test case mentioned above
        wait;
    end process;
    
end Behavioral;

EDA play ground Execution : Click here

Testing the design:

click here to refer the steps to execute the design and test bench on GHDL and GTKWave.

Waveform: