Design 1X8 demux using behavioural style modelling in VHDL and simulate on GHDL and GTKWave open simulator.

Design:

-- 1X8 demux with behavioral style modeling
Library ieee;
use ieee.std_logic_1164.all;

--******** design under test (DUT)*******
--entity part
entity Demux1X8 is
    -- entity interface declaration
    Port (
    i : in STD_LOGIC;                         -- input
    a : in STD_LOGIC_VECTOR (2 downto 0);     -- selection line
    o : out STD_LOGIC_VECTOR (7 downto 0)); -- output
end Demux1X8;

-- architecture part
architecture Behavioral of Demux1X8 is

-- architecture body
begin

-- behavioral logic will realize through the process statement
process (a,i) -- process with sensitivity list
begin
    -- writing demux design from behavior
    -- out put o will define from selection line logic
    -- i will be either 0/1 and assign based on a to o(a) and other will be zero
    if (a = "000") then o<=(0=>i, others => '0'); end if ; -- o(0)=i when a=0
    if (a = "001") then o<=(1=>i, others => '0'); end if ; -- o(1)=i when a=1
    if (a = "010") then o<=(2=>i, others => '0'); end if ; -- o(2)=i when a=2
    if (a = "011") then o<=(3=>i, others => '0'); end if ; -- o(3)=i when a=3
    if (a = "100") then o<=(4=>i, others => '0'); end if ; -- o(4)=i when a=4
    if (a = "101") then o<=(5=>i, others => '0'); end if ; -- o(5)=i when a=5
    if (a = "110") then o<=(6=>i, others => '0'); end if ; -- o(6)=i when a=6
    if (a = "111") then o<=(7=>i, others => '0'); end if ; -- o(7)=i when a=7
end process;
end Behavioral;

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Test bench:

 -- creating test environment for 1X8 demux
Library ieee;
use ieee.std_logic_1164.all;

-- test bench entity
entity tb is
-- usually the test environment has no physical interface
-- Port ( );
end tb;

-- architecture part
architecture Behavioral of tb is

-- declaring DUT as a component of the tb
component Demux1X8

-- component interface
    Port (
        -- usually you need to copy the DUT inteface and paste here
        i : in STD_LOGIC;
        a : in STD_LOGIC_VECTOR (2 downto 0);
        o : out STD_LOGIC_VECTOR (7 downto 0));
end component;

-- declaring test bench interfaces through the signals
signal i : STD_LOGIC;
signal a : STD_LOGIC_VECTOR (2 downto 0);
signal o : STD_LOGIC_VECTOR (7 downto 0);

-- architecture body
begin
-- taking instace of DUT in testbench
-- connection DUT -> TB
--                 i -> i
--    a (2 downto 0)-> a(2 downto 0)
--  o (7 downto 0)-> o(7 downto 0)
a1: Demux1X8 port map (i,a,o);

-- generating test signals through process statement
process -- process with n sensitivity list
-- process body
begin
    -- make the input i always high
    i<='1';
    -- applying all possible combinations at input a
    a <= "000" ; wait for 10 ns;
    a <= "001" ; wait for 10 ns;
    a <= "010" ; wait for 10 ns;
    a <= "011" ; wait for 10 ns;
    a <= "100" ; wait for 10 ns;
    a <= "101" ; wait for 10 ns;
    a <= "110" ; wait for 10 ns;
    a <= "111" ; wait for 10 ns;
    
    -- essential to add the assert fail line to reduce the size of VCD file
    assert false report "end of simulation";
    -- if you are not add this line simulation goes for infinitly
    -- this line stops simulation after all test case mentioned above
    wait;
end process;
end Behavioral;

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Testing the design:

EDA playground link: Click here

click here to refer the steps to execute the design and test bench on GHDL and GTKWave.

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Waveform: