Design and implement the full adder circuit by taking instance of the half adder circuit in structural style modeling in VHDL on GHDL and GTKWave simulator.

Design part:

Library ieee;
use ieee.std_logic_1164.all;

-- ************** design under test (DUT)***************
-- Entity part
entity full_adder_struct is
    Port (
        -- input interface
        a : in STD_LOGIC;
        b : in STD_LOGIC;
        cin : in STD_LOGIC;
        -- out put  interface
        sum : out STD_LOGIC;
        carry : out STD_LOGIC);
end full_adder_struct;

-- architecture part
architecture Behavioral of full_adder_struct is
-- define the half adder as component
    component half_adder
        port (
            -- component input interface
            a : in STD_LOGIC;
            b : in STD_LOGIC;
            -- component output interface
            Sum : out STD_LOGIC;
            carry : out STD_LOGIC);
    end component;

--signals to interconnect
signal x1, x2,x3 : STD_LOGIC;

-- architecture body
begin

ha1: half_adder port map (a,b,x1,x2);        -- first HA instance
ha2: half_adder port map (x1,cin,sum,x3);    -- second HA instance
carry <= x3 or x2;                            -- carry logic
-- end of architecture
end Behavioral; 

Component design (Half adder):

Library ieee;
use ieee.std_logic_1164.all;

-- component entity part
entity Half_adder is
    -- defining interface
    Port (
        -- component input interface
        a : in STD_LOGIC;
        b : in STD_LOGIC;
        -- component output interface
        sum : out STD_LOGIC;
        carry : out STD_LOGIC);
end Half_adder;

-- component architecture part
architecture Behavioral of Half_adder is
-- architecture body
begin
sum <= a xor b;        -- sum is logical xoring of a and b
carry <= a and b;    -- carry is logical anding of a and b   
-- end of component architecture body
end Behavioral;

Test Bench :

Library ieee;
use ieee.std_logic_1164.all;
-- ********** test bench part ***********
-- entity part
entity tb is
-- Port ( ); -- usually no ports are define in testbench
end tb;

-- architecture part
architecture Behavioral of tb is
-- component defination of DUT
    Component full_adder_struct
        -- component interface
        Port (
            -- input interface
            a : in STD_LOGIC;
            b : in STD_LOGIC;
            cin : in STD_LOGIC;
            -- output interface
            sum : out STD_LOGIC;
            carry : out STD_LOGIC);
    end Component;
    
-- test bench interfaces define as signals   
signal a,b,cin,sum,carry : STD_LOGIC;

-- architecture body
begin

a1: full_adder_struct port map (a,b,cin,sum,carry); -- taking instance of component

-- define all possible combinations for 3 inputs
process
begin
a<= '0';b<= '0';cin<= '0'; wait for 10 ns;
a<= '0';b<= '0';cin<= '1'; wait for 10 ns;
a<= '0';b<= '1';cin<= '0'; wait for 10 ns;
a<= '0';b<= '1';cin<= '1'; wait for 10 ns;
a<= '1';b<= '0';cin<= '0'; wait for 10 ns;
a<= '1';b<= '0';cin<= '1'; wait for 10 ns;
a<= '1';b<= '1';cin<= '0'; wait for 10 ns;
a<= '1';b<= '1';cin<= '1'; wait for 10 ns;
assert false report "end of simulation";
wait;
end process;
-- end of architecture body
end Behavioral;

EDA playground link for execution: Click here

Steps to execute the codes:

Error checking
1) ghdl –s ha.vhd --for error in code. If no massage display no error.
2) ghdl –s fa.vhd --for error in code. If no massage display no error.
3) ghdl –s fa_tb.vhd --for error in test bench. If no massage display no error.

Analyze
3) ghdl –a fa.vhd --for analyse code. If no massage display no error.
4) ghdl –a fa_tb.vhd --for analyse test bench. If no massage display no error.

Create executable
5) ghdl –e tb  --for create executable and we need to mention name of testbench's entity.

Run executable
6) ghdl –r tb --vcd=ha.vcd -- run and creat vcd file for half_adder.

Launch gtkwave
7) gtkwave ha.vcd --- launch gtkwave and vcd created for alf_adder_tb.

Waveform: