Design and implement all basic gates in VHDL on simuator GHDL and GTKWave.

Design file:

 Library ieee;
use ieee.std_logic_1164.all;
-- ************Design under test (DUT)**************
-- Entity part
entity basic_gates is
    Port (
    -- port defination
        a : in STD_LOGIC;        
        b : in STD_LOGIC;
        and2 : out STD_LOGIC;
        or2 : out STD_LOGIC;
        nand2 : out STD_LOGIC;
        nor2 : out STD_LOGIC;
        xor2 : out STD_LOGIC;
        not1 : out STD_LOGIC;
        xnor2 : out STD_LOGIC);
end basic_gates;

-- Architecture part
architecture Behavioral of basic_gates is
    begin
        and2 <= a and b;            -- logical anding
        or2 <= a or b;                -- logical oring
        nand2 <= not (a and b);        -- logical nanding
        nor2 <= not (a or b);        -- logical noring
        xor2 <= a xor b;            -- logical exoring
        xnor2 <= not (a xor b);        -- logical exnoring
        not1 <= not a;                -- logical inversion
end Behavioral;

Test bench:

entity testbench is
-- Port ( );        
end testbench;

-- Architecture part
architecture Behavioral of testbench is
            -- define DUT inform of component here
            component basic_gates
                Port (
                    a : in STD_LOGIC;
                    b : in STD_LOGIC;
                    and2 : out STD_LOGIC;
                    or2 : out STD_LOGIC;
                    nand2 : out STD_LOGIC;
                    nor2 : out STD_LOGIC;
                    xor2 : out STD_LOGIC;
                    not1 : out STD_LOGIC;
                    xnor2 : out STD_LOGIC);
            end component;

-- Test bench interfaces always defined in form of signals       
signal a,b,and2 ,or2 ,nand2 ,nor2 ,xor2,not1 ,xnor2 : STD_LOGIC;

-- Architecture body
    begin
-- Take instance of the component/DUT
    Inst: basic_gates port map (a,b,and2 ,or2 ,nand2 ,nor2 ,xor2,not1 ,xnor2);

--Concurrent signals defined in process
process
begin
--define all possible combination for two inputs
a<='0';b<='0'; wait for 10 ns;
a<='0';b<='1'; wait for 10 ns;
a<='1';b<='0'; wait for 10 ns;
a<='1';b<='1'; wait for 10 ns;
assert false report "end of simulation";
wait;
end process;
end Behavioral;

EDA palyground link : Click here

Steps to execute code:

Error checking
1) ghdl –s basic_gates.vhd --for error in code. If no massage display no error.
2) ghdl –s basic_gates_tb.vhd --for error in test bench. If no massage display no error.

Analyze
3) ghdl –a basic_gates.vhd --for analyse code. If no massage display no error.
4) ghdl –a basic_gates_tb.vhd --for analyse test bench. If no massage display no error.

Create executable
5) ghdl –e testbench  --for create executable and we need to mention name of testbench's entity.

Run executable
6) ghdl –r testbench --vcd=bg.vcd -- run and creat vcd file for half_adder.

Launch gtkwave
7) gtkwave bg.vcd --- launch gtkwave and vcd created for alf_adder_tb.

Waveform: